The present invention relates to the delay of timing signals in an integrated circuit, and in particular for an analog front end (AFE) chip.
A typical imaging system has the elements shown in FIG. 1. A charged coupled device (CCD) chip 12 provides an analog CCD output on line 14 under the control of timing signals on lines 16 from a timing generator chip 18. The timing generator also provides timing signals on lines 20 to AFE chip 22. Chip 22 digitizes the data, and provides a digital data output on lines 24 to a digital signal processing (DSP) chip 26. DSP chip 26 provides control signals on lines 28 to AFE 22.
The AFE amplifies and digitizes the CCD analog output signal. The DSP is used to process the digitized CCD data into an image.
The timing signals on lines 20 for the AFE usually consist of three signals, as illustrated in FIG. 2: SPIX, SBLK and ADCCLOCK. The SPIX samples the video signal. The SBLK samples the black signal which is used to establish a calibration reference. The ADCCLOCK is used to time the digitization in the AFE.
It is desirable to be able to optimize the placement of these timing signals shown in FIG. 2. In particular, there are many different CCD chips and AFE chips in the marketplace with different characteristics.
In an existing product marketed by the assignee of the present application, Exar""s AFE chip 9855 provides a programmable delay in the AFE chip. The delay is programmed using the serial port control lines 28 shown in FIG. 1. However, this delay merely allows the signals to be delayed with their existing pulse widths, and does not allow the pulse width to be varied.
In other technology areas, pulses can be varied in both position and width. Examples are set forth in U.S. Pat. Nos. 5,008,563 and 5,589,788.
The present invention provides a programmable delay in an AFE of an imaging system which can vary both the pulse position and the pulse width. The pulse width and position are controlled by providing separate programmable delay circuits for the rising and falling edges of the desired timing signal. Combining logic then combines the outputs of the two delay circuits to produce an output clock with separately delayed rising and falling edges.
In a preferred embodiment, the delay circuits each have a number of taps providing different delayed versions of the pulse. Multiplexer circuits allow the selection of the desired delay for both delay circuits. A comparison circuit compares the programmed rising and falling edges. The invention provides a simple logic implementation for the delayed tap structure. The delayed pulses can simply be combined in one of two manners depending on whether the rising edge delay desired is greater or less than the desired falling edge delay. If the rising edge delay is greater than the falling edge delay, an AND function is selected in the combining logic. On the other hand, if the rising edge delay is less than the falling edge delay, an OR function is selected in the combining circuit. The selection is done automatically in response to the programmed rising and falling edge delays as selected by the DSP serial input.
For a further understanding of the nature and advantages of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings.